EP2SGX60CF780C4N Datasheet, PDF (296/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Table 4–105. Maximum DCD for DDIO Output on Column I/O Pins With PLL in
the Clock Path (Part 2 of 2)
Maximum DCD (ps) for ^{Stratix II GX Devices (PLL Output Feeding}
Column DDIO Output I/O
DDIO)
Unit
Standard
-3 Device
-4 and -5 Device
1.2-V HSTL
155
155
ps
LVPECL
180
180
ps
High-Speed I/O
Specifications
Table 4–106 provides high-speed timing specifications definitions.
Table 4–106. High-Speed Timing Specifications and Definitions
High-Speed Timing Specifications
Definitions
t_C
f_{H S C L K}
J
W
t_{R I S E}
t_{F A L L}
Timing unit interval (TUI)
f_IN
f_{H S D R}
f_{H S D R D P A}
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter
Output jitter
t_DUTY
t_{L O C K}
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Deserialization factor (width of parallel data bus).
PLL multiplication factor.
Low-to-high transmission time.
High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = t_C /w).
Fast PLL input clock frequency
Maximum/minimum LVDS data transfer rate (f_{H SD R} = 1/TUI), non-DPA.
Maximum/minimum LVDS data transfer rate (f_{H S D R D PA} = 1/TUI), DPA.
The timing difference between the fastest and the slowest output edges
including t_CO variation and clock skew across channels driven by the
same fast PLL. The clock is included in the TCCS measurement.
The period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.