EP2SGX60CF780C4N Datasheet, PDF (211/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

DC and Switching Characteristics
Table 4–22. PCS Latency (Part 3 of 3) Note (1)
Functional
Mode
Configuration
Word
Aligner
Deskew
FIFO
Rate
Matcher
(3)
Receiver PCS Latency
8B/10B
Decoder
Receiver Byte
State
De-
Machine serializer
16/20-bit 4-5
-
11-13
1
-
1
channel
width; with
Rate
Matcher
16/20-bit 4-5
-
-
1
-
1
channel
width;
without
Rate
BASIC _Matcher
Double
Width
32/40-bit 2-2.5
-
5.5-6.5 0.5
-
1
channel
width; with
Rate
Matcher
32/40-bit 2-2.5 -
-
0.5
-
1
channel
width;
without
Rate
Matcher
Byte
Order
1
1
1
1-3
Receiver
Phase
Comp
FIFO
1-2
Receiver Sum
PIPE
(2)
- 19-23
1-2
-
8-10
1-2
- 11-14
1-2
-
6-9
Notes to Table 4–21:
(1) The latency numbers are with respect to the PLD-transceiver interface clock cycles.
(2) The total latency number is rounded off in the Sum column.
(3) The rate matcher latency shown is the steady state latency. Actual latency may vary depending on the skip ordered set
gap allowed by the protocol, actual PPM difference between the reference clocks, and so forth.
(4) For CPRI 614 Mbps and 1.228 Gbps data rates, the Quartus II software customizes the PLD-transceiver interface clocking
to achieve zero clock cycle uncertainty in the receiver phase compensation FIFO latency. For more details, refer to the CPRI
Mode section in the Stratix II GX Transceiver Architecture Overview chapter in volume 2 of the Stratix II GX Device Handbook
Altera Corporation
June 2009
4–41
Stratix II GX Device Handbook, Volume 1