EP2SGX60CF780C4N Datasheet, PDF (50/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Transceivers
f
The dynamic reconfiguration block can dynamically reconfigure the
following PMA settings:
■ Pre-emphasis settings
■ Equalizer and DC gain settings
■ Voltage Output Differential (V_OD) settings
The channel reconfiguration allows you to dynamically modify the data
rate, local dividers, and the functional mode of the transceiver channel.
Refer to the Stratix II GX Device Handbook, volume 2, for more
information.
The dynamic reconfiguration block requires an input clock between
2.5 MHz and 50 MHz. The clock for the dynamic reconfiguration block is
derived from a high-speed clock and divided down using a counter.
Individual Power Down and Reset for the Transmitter and Receiver
Stratix II GX transceivers offer a power saving advantage with their
ability to shut off functions that are not needed. The device can
individually reset the receiver and transmitter blocks and the PLLs. The
Stratix II GX device can either globally or individually power down and
reset the transceiver. Table 2–16 shows the connectivity between the reset
signals and the Stratix II GX transceiver blocks. These reset signals can be
controlled from the FPGA or pins.
2–42
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007