EP2SGX60CF780C4N Datasheet, PDF (113/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Stratix II GX Architecture
Figure 2–73 shows the global and regional clocking from enhanced PLL
outputs and top and bottom CLK pins.
Figure 2–73. Global and Regional Clock Connections from Top and Bottom Clock Pins and Enhanced PLL
Outputs Notes (1), (2)
CLK13 CLK15
(2) CLK12 CLK14
(2)
PLL11_FB
PLL5_FB
PLL11_OUT[2..0]p
PLL11_OUT[2..0]n
Regional
Clocks
RCLK27
RCLK26
RCLK25
RCLK24
Global
Clocks
Regional
Clocks
RCLK8
RCLK9
RCLK10
RCLK11
PLL12_OUT[2..0]p
PLL12_OUT[2..0]n
PLL 11
PLL 5
c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5
PLL5_OUT[2..0]p
PLL5_OUT[2..0]n
RCLK31
RCLK30
RCLK29
RCLK28
G15
G14
G13
G12
G4
G5
G6
G7
c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5
PLL 12
PLL 6
RCLK12
RCLK13
RCLK14
RCLK15
PLL6_OUT[2..0]p
PLL6_OUT[2..0]n
PLL12_FB
(2) _CLK4
CLK6
PLL6_FB
(2)
CLK5
CLK7
Notes to Figure 2–73:
(1) EP2SGX30C/D and EP2SGX60C/D devices only have two enhanced PLLs (5 and 6), but the connectivity from these
two PLLs to the global and regional clock networks remains the same as shown.
(2) If the design uses the feedback input, you will lose one (or two, if FBIN is differential) external clock output pin.
Altera Corporation
October 2007
2–105
Stratix II GX Device Handbook, Volume 1