EP2SGX60CF780C4N Datasheet, PDF (108/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

PLLs and Clock Networks
Figure 2–70 shows a top-level diagram of the Stratix II GX device and PLL
floorplan.
Figure 2–70. PLL Locations
FPLL7CLK 7
CLK[15..12]
11 5
1
CLK[3..0]
2
PLLs
FPLL8CLK 8
12 6
CLK[7..4]
Figures 2–71 and 2–72 shows global and regional clocking from the fast
PLL outputs and the side clock pins. The connections to the global and
regional clocks from the fast PLL outputs, internal drivers, and the CLK
pins on the left side of the device are shown in Table 2–27.
2–100
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007