EP2SGX60CF780C4N Datasheet, PDF (107/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Stratix II GX Architecture
Table 2–26 shows the enhanced PLL and fast PLL features in Stratix II GX
devices.
Table 2–26. Stratix II GX PLL Features
Feature
Enhanced PLL
Clock multiplication and division
m/(n × post-scale counter) (1)
Phase shift
Clock switchover
Down to 125-ps increments (3), (4)
v
PLL reconfiguration
v
Reconfigurable bandwidth
v
Spread spectrum clocking
v
Programmable duty cycle
v
Number of internal clock outputs
6
Number of external clock outputs Three differential/six single-ended
Number of feedback clock inputs
One single-ended or differential
(7), (8)
Fast PLL
m/(n × post-scale counter) (2)
Down to 125-ps increments (3), (4)
v (5)
v
v
v
4
(6)
Notes to Table 2–26:
(1) For enhanced PLLs, m, n range from 1 to 256 and post-scale counters range from 1 to 512 with 50% duty cycle.
(2) For fast PLLs, m, and post-scale counters range from 1 to 32. The n counter ranges from 1 to 4.
(3) The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8.
(4) For degree increments, Stratix II GX devices can shift all output frequencies in increments of at least 45. Smaller
degree increments are possible depending on the frequency and divide parameters.
(5) Stratix II GX fast PLLs only support manual clock switchover.
(6) Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data
channel to generate txclkout.
(7) If the feedback input is used, you will lose one (or two, if f_BIN is differential) external clock output pin.
(8) Every Stratix II GX device has at least two enhanced PLLs with one single-ended or differential external feedback
input per PLL.
Altera Corporation
October 2007
2–99
Stratix II GX Device Handbook, Volume 1