EP2SGX60CF780C4N Datasheet, PDF (65/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Stratix II GX Architecture
Figure 2–42. Conditional Operation Example
ALM 1
Adder output
is not used.
X[0]
Y[0]
syncdata
X[1]
Y[1]
Carry Chain
Comb & _X[0]
Adder
Logic
Comb &
Adder
Logic
syncload
X[1]
syncload
R[0]
DQ
reg0
R[1]
DQ
reg1
ALM 2
To general or
local routing
To general or
local routing
X[2]
Comb &
Adder ^X[2]
Y[2]
Logic
R[2]
DQ
To general or
local routing
syncload
reg0
Comb &
Adder
Logic
carry_out
To local routing &
then to LAB-wide
syncload
The arithmetic mode also offers clock enable, counter enable,
synchronous up and down control, add and subtract control,
synchronous clear, synchronous load. The LAB local interconnect data
inputs generate the clock enable, counter enable, synchronous up and
down and add and subtract control signals. These control signals may be
used for the inputs that are shared between the four LUTs in the ALM.
The synchronous clear and synchronous load options are LAB-wide
signals that affect all registers in the LAB. The Quartus II software
automatically places any registers that are not used by the counter into
other LABs.
Altera Corporation
October 2007
2–57
Stratix II GX Device Handbook, Volume 1