EP2SGX60CF780C4N Datasheet, PDF (174/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Operating Conditions
Table 4–5. Stratix II GX Transceiver Block Operating Conditions
Symbol
V_CCA
V_CCP
V_CCR
V_CCT
V_{CCT_B}
V_CCL
V_{CCH_B} (2)
R_REF (1)
Parameter
Transceiver block supply
voltage
Transceiver block supply
voltage
Transceiver block supply
voltage
Transceiver block supply
voltage
Transceiver block supply
voltage
Transceiver block supply
voltage
Transceiver block supply
voltage
Reference resistor
Conditions
Commercial
and industrial
Commercial
and industrial
Commercial
and industrial
Commercial
and industrial
Commercial
and industrial
Commercial
and industrial
Commercial
and industrial
Commercial
and industrial
Minimum
3.135
Typical Maximum Units
3.3
3.465
V
1.15
1.2
1.25
V
1.15
1.2
1.25
V
1.15
1.2
1.25
V
1.15
1.2
1.25
V
1.15
1.2
1.25
V
1.15
1.425
2000 –1%
1.2
1.25
V
1.5
1.575
V
2000 2000 +1% Ω
Notes to Table 4–5:
(1) The DC signal on this pin must be as clean as possible. Ensure that no noise is coupled to this pin.
(2) Refer to the Stratix II GX Device Handbook, volume 2, for more information.
Table 4–6. Stratix II GX Transceiver Block AC Specification (Part 1 of 6)
Symbol /
Description
Conditions
-3 Speed Commercial
Speed Grade
Min Typ Max
-4 Speed Commercial
and Industrial Speed
Grade
-5 Speed Commercial
Speed Grade
Unit
Min Typ Max Min Typ Max
Reference clock
Input
frequency from
REFCLK input
50
- 622.08 50
- 622.08 50
- 622.08 MHz
Input
frequency from
PLD input
Input clock
jitter
Absolute V_{M A X}
for a REFCLK
pin (12)
50
-
325
50
-
325 50
-
325 MHz
Refer to Table 4–20 on page 4–36 for the input jitter specifications for the
reference clock.
-
-
3.3
-
-
3.3
-
-
3.3
V
4–4
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009