EP2SGX60CF780C4N Datasheet, PDF (192/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Operating Conditions
Table 4–19. Stratix II GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 5 of 19)
Symbol/
Description
Conditions
-3 Speed
Commercial Speed
Grade
-4 Speed
Commercial and
Industrial Speed
Grade
-5 Speed
Commercial Speed
Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
Peak-to-peak jitter Jitter frequency =
22.1 KHz
> 8.5
> 8.5
> 8.5
UI
Peak-to-peak jitter Jitter frequency =
1.875 MHz
> 0.1
> 0.1
> 0.1
UI
Peak-to-peak jitter Jitter frequency = 20
MHz
> 0.1
> 0.1
> 0.1
UI
PCI Express Transmit Jitter Generation (10)
Total jitter at 2.5 Compliance pattern -
Gbps
V_OD = 800 mV
Pre-emphasis
(1st post-tap) =
Setting 5
- 0.25 -
- 0.25 -
- 0.25 UI
PCI Express Receiver Jitter Tolerance (10)
Total jitter at 2.5
Gbps
Compliance pattern
No Equalization
DC gain = 3 dB
> 0.6
> 0.6
> 0.6
UI
Serial RapidIO Transmit Jitter Generation (11)
Deterministic Jitter Data Rate = 1.25,
-
(peak-to-peak) 2.5, 3.125 Gbps
REFCLK = 125 MHz
Pattern = CJPAT
V_OD = 800 mV
No Pre-emphasis
- 0.17 -
- 0.17 -
- 0.17 UI
Total Jitter
(peak-to-peak)
Data Rate = 1.25,
-
2.5, 3.125 Gbps
REFCLK = 125 MHz
Pattern = CJPAT
V_OD = 800 mV
No Pre-emphasis
- 0.35 -
- 0.35 -
- 0.35 UI
4–22
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009