EP2SGX60CF780C4N Datasheet, PDF (226/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Operating Conditions
Bus Hold Specifications
Table 4–48 shows the Stratix II GX device family bus hold specifications.
Table 4–48. Bus Hold Parameters
Parameter Conditions
1.2 V
1.5 V
V_CCIO Level
1.8 V
2.5 V
3.3 V Unit
Low
sustaining
current
High
sustaining
current
Low
overdrive
current
High
overdrive
current
Bus-hold
trip point
V_IN > V_IL
(maximum)
V_IN < V_IH
(minimum)
0 V < V_IN <
V_CCIO
0 V < V_IN <
V_CCIO
Min Max Min Max Min Max Min Max Min Max
22.5
25
30
50
70
μA
–22.5
–25
–30
–50
–70
μA
120
160
200
300
500 μA
–120
–160
–200
–300
–500 μA
0.45 0.95 0.5 1.0 0.68 1.07 0.7 1.7 0.8 2.0 V
On-Chip Termination Specifications
Tables 4–49 and 4–50 define the specification for internal termination
resistance tolerance when using series or differential on-chip termination.
Table 4–49. On-Chip Termination Specification for Top and Bottom I/O Banks (Part 1 of 2) Notes (1), (2)
Symbol
Description
Conditions
25-Ω R_S
3.3/2.5
50-Ω R_S
3.3/2.5
Internal series termination with
calibration (25-Ω setting)
V_CCIO = 3.3/2.5 V
Internal series termination without V_CCIO = 3.3/2.5 V
calibration (25-Ω setting)
Internal series termination with
calibration (50-Ω setting)
V_CCIO = 3.3/2.5 V
Internal series termination without V_CCIO = 3.3/2.5 V
calibration (50-Ω setting)
Resistance Tolerance
Commercial Industrial
Max
Max
Unit
±5
±10
%
±30
±30
%
±5
±10
%
±30
± 30
%
4–56
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009