EP2SGX60CF780C4N Datasheet, PDF (97/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Stratix II GX Architecture
PLLs and Clock
Networks
Stratix II GX devices provide a hierarchical clock structure and multiple
phase-locked loops (PLLs) with advanced features. The large number of
clocking resources in combination with the clock synthesis precision
provided by enhanced and fast PLLs provides a complete clock
management solution.
Global and Hierarchical Clocking
Stratix II GX devices provide 16 dedicated global clock networks and
32 regional clock networks (eight per device quadrant). These clocks are
organized into a hierarchical clock structure that allows for up to 24 clocks
per device region with low skew and delay. This hierarchical clocking
scheme provides up to 48 unique clock domains in Stratix II GX devices.
There are 12 dedicated clock pins to drive either the global or regional
clock networks. Four clock pins drive each side of the device, as shown in
Figures 2–61 and 2–62. Internal logic and enhanced and fast PLL outputs
can also drive the global and regional clock networks. Each global and
regional clock has a clock control block, which controls the selection of the
clock source and dynamically enables or disables the clock to reduce
power consumption. Table 2–24 shows global and regional clock features.
Table 2–24. Global and Regional Clock Features
Feature
Number per device
Number available per
quadrant
Sources
Dynamic clock source
selection
Dynamic enable/disable
Global Clocks
16
16
Regional Clocks
32
8
Clock pins, PLL outputs,
core routings,
inter-transceiver clocks
v
Clock pins, PLL outputs,
core routings,
inter-transceiver clocks
—
v
v
Global Clock Network
These clocks drive throughout the entire device, feeding all device
quadrants. The global clock networks can be used as clock sources for all
resources in the device IOEs, ALMs, DSP blocks, and all memory blocks.
These resources can also be used for control signals, such as clock enables
and synchronous or asynchronous clears fed from the external pin. The
global clock networks can also be driven by internal logic for internally
Altera Corporation
October 2007
2–89
Stratix II GX Device Handbook, Volume 1