EP2SGX60CF780C4N Datasheet, PDF (114/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

PLLs and Clock Networks
The connections to the global and regional clocks from the top clock pins
and enhanced PLL outputs are shown in Table 2–28. The connections to
the clocks from the bottom clock pins are shown in Table 2–29.
Table 2–28. Global and Regional Clock Connections from Top Clock Pins and Enhanced PLL Outputs
(Part 1 of 2)
Top Side Global and
Regional Clock Network
Connectivity
Clock pins
CLK12p
vvv
v
v
CLK13p
vvv
v
v
CLK14p
v
vv
v
v
CLK15p
v
vv
v
v
CLK12n
v
v
v
CLK13n
v
v
v
CLK14n
CLK15n
v
v
v
v
v
v
Drivers from internal logic
GCLKDRV0
v
GCLKDRV1
v
GCLKDRV2
v
GCLKDRV3
v
RCLKDRV0
v
v
RCLKDRV1
v
v
RCLKDRV2
RCLKDRV3
RCLKDRV4
v
v
v
v
v
v
RCLKDRV5
v
v
RCLKDRV6
v
v
RCLKDRV7
v
v
Enhanced PLL5 outputs
c0
vvv
v
v
c1
vvv
v
v
2–106
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007