EP2SGX60CF780C4N Datasheet, PDF (148/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

High-Speed Differential I/O with DPA Support
Figure 2–89 shows the block diagram of the Stratix II GX receiver channel.
Figure 2–89. Stratix II GX Receiver Channel
Up to 1 Gbps ⁺
–
DQ
Data Realignment
Circuitry
Data to R4, R24, C4, or
direct link interconnect
10
data retimed_data
DPA
DPA_clk
Eight Phase Clocks
8
refclk
Fast
PLL
Synchronizer
diffioclk
load_en
Dedicated
Receiver
Interface
Regional or
global clock
f
An external pin or global or regional clock can drive the fast PLLs, which
can output up to three clocks: two multiplied high-speed clocks to drive
the SERDES block and/or external pin, and a low-speed clock to drive the
logic array. In addition, eight phase-shifted clocks from the VCO can feed
to the DPA circuitry.
For more information on the fast PLL, see the PLLs in Stratix II GX
Devices chapter in volume 2 of the Stratix II GX Handbook.
The eight phase-shifted clocks from the fast PLL feed to the DPA block.
The DPA block selects the closest phase to the center of the serial data eye
to sample the incoming data. This allows the source-synchronous
circuitry to capture incoming data correctly regardless of the
channel-to-channel or clock-to-channel skew. The DPA block locks to a
phase closest to the serial data phase. The phase-aligned DPA clock is
used to write the data into the synchronizer.
The synchronizer sits between the DPA block and the data realignment
and SERDES circuitry. Since every channel utilizing the DPA block can
have a different phase selected to sample the data, the synchronizer is
needed to synchronize the data to the high-speed clock domain of the
data realignment and the SERDES circuitry.
2–140
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007