EP2SGX60CF780C4N Datasheet, PDF (74/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

MultiTrack Interconnect
Figure 2–47. Shared Arithmetic Chain, Carry Chain and Register Chain Interconnects
Local Interconnect
Routing Among ALMs
in the LAB
Carry Chain & Shared
Arithmetic Chain
Routing to Adjacent ALM
Local
Interconnect
ALM 1
ALM 2
Register Chain
Routing to Adjacent
ALM's Register Input
ALM 3
ALM 4
ALM 5
ALM 6
ALM 7
ALM 8
The C4 interconnects span four LABs, M512, or M4K blocks up or down
from a source LAB. Every LAB has its own set of C4 interconnects to drive
either up or down. Figure 2–48 shows the C4 interconnect connections
from a LAB in a column. The C4 interconnects can drive and be driven by
all types of architecture blocks, including DSP blocks, TriMatrix memory
blocks, and column and row IOEs. For LAB interconnection, a primary
LAB or its LAB neighbor can drive a given C4 interconnect. C4
interconnects can drive each other to extend their range as well as drive
row interconnects for column-to-column connections.
2–66
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007