EP2SGX60CF780C4N Datasheet, PDF (310/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Table 4–118. Document Revision History (Part 4 of 5)
Date and
Document
Version
Changes Made
Summary of Changes
June 2006, v4.0
● Updated Table 6–5.
● Updated Table 6–6.
● Updated all values in Table 6–7.
● Added Tables 6–8 and 6–9.
● Added Figures 6–1 through 6–4.
● Updated Table 6–18.
● Updated Tables 6–85 through 6–96.
● Added Table 6–80, Stratix II GX Maximum
Output Clock Rate for Dedicated Clock Pins.
● Updated Table 6–100.
● In “I/O Timing Measurement Methodology”
section, updated Table 6–42.
● In “Internal Timing Parameters” section,
updated Tables 6–43 through 6–48.
● In “Stratix II GX Clock Timing Parameters”
section, updated Tables 6–50 through 6–65.
● In “IOE Programmable Delay” section, updated
Tables 6–67 and 6–68.
● In “I/O Delays” section, updated Tables 6–71
through 6–74.
● In “Maximum Input & Output Clock Toggle Rate”
section, updated Tables 6–75 through 6–83.
● In “DCD Measurement Techniques” section,
updated Tables 6–85 through 6–92.
● In “High-Speed I/O Specifications” section,
updated Tables 6–94 through 6–96.
● In “External Memory Interface Specifications”
section, updated Table 6–100.
● Removed rows for V_{I D}, V_{O D}, V_{I C M} ,
and V_{O C M} from Table 6–5.
● Updated values for rx, tx, and
refclkb in Table 6–6.
● Removed table containing 1.2-V
PCML I/O information. That
information is in Table 6–7.
● Added values to Table 6–100.