EP2SGX60CF780C4N Datasheet, PDF (238/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Timing Model
Table 4–55. Stratix II GX Performance Notes (Part 3 of 3) Note (1)
Resources Used
Performance
Applications
TriMatrix Single port RAM
Memory 64K x 9 bit
MegaRAM _Simple
block
dual-port RAM
(cont.)
64K x 9 bit
True dual-port
RAM 64K x 9 bit
DSP
block
9 x 9-bit
multiplier (5)
18 x 18-bit
multiplier (5)
18 x 18-bit
multiplier (7)
36 x 36-bit
multiplier (5)
36 x 36-bit
multiplier (6)
18-bit, 4-tap FIR
filter
ALUTs
0
0
0
0
0
0
0
0
0
TriMatrix
Memory
Blocks
DSP
Blocks
-3 Speed
Grade
(2)
1
0
364.96
1
0
420.16
1
0
359.71
0
1
430.29
0
1
410.17
0
1
450.04
0
1
250.0
0
1
410.17
0
1
410.17
-3
Speed
Grade
(3)
-4 Speed
Grade
347.22 325.73
400.0 375.93
342.46 322.58
409.16 385.2
390.01 367.1
428.08 403.22
238.15 224.01
390.01 367.1
390.01 367.1
-5
Speed Units
Grade
271.73 MHz
313.47 MHz
268.09 MHz
320.1 MHz
305.06 MHz
335.12 MHz
186.6 MHz
305.06 MHz
305.06 MHz
Notes to Table 4–55:
(1) These design performance numbers were obtained using the Quartus II software.
(2) This column refers to -3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
(3) This column refers to -3 speed grades for EP2SGX130 devices.
(4) This application uses registered inputs and outputs.
(5) This application uses registered multiplier input and output stages within the DSP block.
(6) This application uses registered multiplier input, pipeline, and output stages within the DSP block.
(7) This application uses registered multiplier inputs with outputs of the multiplier stage feeding the accumulator or
subtractor within the DSP block.
4–68
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009