EP2SGX60CF780C4N Datasheet, PDF (219/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

DC and Switching Characteristics
Table 4–32. LVPECL Specifications
Symbol
Parameter
Conditions
V_CCIO (1)
V_ID
I/O supply voltage
Input differential voltage
swing (single-ended)
V_ICM
V_OD
V_OCM
Input common mode voltage
Output differential voltage
(single-ended)
R_L = 100 Ω
Output common mode
voltage
R_L = 100 Ω
R_L
Receiver differential input
resistor
Minimum
3.135
300
1.0
525
1,650
90
Typical
3.3
600
100
Maximum Unit
3.465
V
1,000 mV
2.5
V
970
mV
2,250 mV
110
Ω
Note to Table 4–32:
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V_CCINT, not V_CCIO.
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
Table 4–33. 3.3-V PCI Specifications
Symbol
Parameter
V_CCIO
V_IH
V_IL
V_OH
V_OL
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Conditions
I_OUT = –500 μA
I_OUT = 1,500 μA
Minimum
3.0
0.5 V_CCIO
–0.3
0.9 V_CCIO
Typical
3.3
Maximum Unit
3.6
V
V_CCIO + 0.5 V
0.3 V_CCIO
V
V
0.1 V_CCIO
V
Table 4–34. PCI-X Mode 1 Specifications
Symbol
Parameter
V_CCIO
V_IH
V_IL
V_IPU
V_OH
V_OL
Output supply voltage
High-level input voltage
Low-level input voltage
Input pull-up voltage
High-level output voltage
Low-level output voltage
Conditions
I_OUT = –500 μA
I_OUT = 1,500 μA
Minimum
3.0
0.5 V_CCIO
–0.3
0.7 V_CCIO
0.9 V_CCIO
Typical
Maximum Unit
3.6
V
V_CCIO + 0.5 V
0.35 V_CCIO V
V
V
0.1 V_CCIO
V
Altera Corporation
June 2009
4–49
Stratix II GX Device Handbook, Volume 1