EP2SGX60CF780C4N Datasheet, PDF (46/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Transceivers
Figure 2–31. Stratix II GX Receiver PLL Recovered Clock to Regional Clock
Connection Notes (1), (2)
CLK[15..12]
11 5
7
RCLK
RCLK
[31..28]
[27..24]
RCLK
[3..0]
RCLK
[23..20]
Stratix II GX
Transceiver
Block
1
CLK[3..0]
2
RCLK
[7..4]
RCLK
[19..16]
Stratix II GX
Transceiver
Block
RCLK
RCLK
8
[11..8]
[15..12]
12 6
CLK[7..4]
Notes to Figure 2–31:
(1) CLK# pins are clock pins and their associated number. These are pins for global
and local clocks.
(2) RCLK# pins are regional clock pins.
2–38
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007