EP2SGX60CF780C4N Datasheet, PDF (245/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

DC and Switching Characteristics
Table 4–61. M-RAM Block Internal Timing Microparameters (Part 2 of 2) Note (1)
Symbol
Parameter
t_MEGABESU
Byte enable setup time
before clock
t_MEGABEH
Byte enable hold time
after clock
t_MEGADATAASU A port data setup time
before clock
t_MEGADATAAH A port data hold time
after clock
t_MEGAADDRASU A port address setup
time before clock
t_MEGAADDRAH A port address hold
time after clock
t_MEGADATABSU B port setup time
before clock
t_MEGADATABH B port hold time after
clock
t_MEGAADDRBSU B port address setup
time before clock
t_MEGAADDRBH B port address hold
time after clock
t_MEGADATACO1 Clock-to-output delay
when using output
registers
t_MEGADATACO2 Clock-to-output delay
without output
registers
t_MEGACLKL
Minimum clock low
time
t_MEGACLKH
Minimum clock high
time
t_MEGACLR
Minimum clear pulse
width
-3 Speed
Grade (2)
Min Max
-9
39
50
243
589
-347
50
243
589
-347
480 715
1950 2899
1250
1250
144
-3 Speed
Grade (3)
Min Max
-10
40
52
255
618
-365
52
255
618
-365
480 749
1950 3042
1312
1312
151
-4 Speed
Grade
Min Max
-11
43
55
271
657
-388
55
271
657
-388
480 797
1950 3235
1395
1395
160
-5 Speed
Grade _Unit
Min Max
-13
ps
52
ps
67
ps
325
ps
789
ps
-465
ps
67
ps
325
ps
789
ps
-465
ps
480 957 ps
1950 3884 ps
1675
ps
1675
ps
192
ps
(1) The M512 block f_MAX obtained using the Quartus II software does not necessarily equal to 1/TMEGARC.
(2) This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
(3) This column refers to –3 speed grades for EP2SGX130 devices.
Altera Corporation
June 2009
4–75
Stratix II GX Device Handbook, Volume 1