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EP2SGX60CF780C4N Datasheet, PDF (7/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards | |||
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Introduction
Table 1â3. Stratix II GX FineLine BGA Package Sizes
Dimension
Pitch (mm)
Area (mm2)
Length width (mm à mm)
780 Pins
1.00
841
29 Ã 29
1,152 Pins
1.00
1,225
35 Ã 35
1,508 Pins
1.00
1,600
40 Ã 40
Referenced
Document
This chapter references the following document:
â Stratix II GX Architecture chapter in volume 1 of the Stratix II GX
Device Handbook
Document
Table 1â4 shows the revision history for this chapter.
Revision History
Table 1â4. Document Revision History
Date and Document
Version
Changes Made
Summary of Changes
October 2007, v1.6 Updated âFeaturesâ section.
Minor text edits.
August 2007, v1.5
Added âReferenced Documentsâ section.
Minor text edits.
February 2007, v1.4 â Changed 622 Mbps to 600 Mbps on
page 1-2 and Table 1â1.
â Deleted âDC couplingâ from the
Transceiver Block Features list.
â Changed 4 to 6 in the PLLs row
(columns 3 and 4) of Table 1â1.
Added the âDocument Revision Historyâ
section to this chapter.
June 2006, v1.3
â Updated Table 1â2.
April 2006, v1.2
â Updated Table 1â1.
â Updated Table 1â2.
February 2006, v1.1 â Updated Table 1â1.
October 2005
v1.0
Added chapter to the Stratix II GX Device
Handbook.
Added support information for the
Stratix II GX device.
Updated numbers for receiver channels and
user I/O pin counts in Table 1â2.
Altera Corporation
October 2007
1â5
Stratix II GX Device Handbook, Volume 1
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