EP2SGX60CF780C4N Datasheet, PDF (42/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Transceivers
Figure 2–27 show the Stratix II GX block in reverse serial pre-CDR
loopback mode.
Figure 2–27. Stratix II GX Block in Reverse Serial Pre-CDR Loopback Mode
Transmitter Digital Logic
BIST
Incremental
Generator
BIST
PRBS
Generator
Analog Receiver and
Transmitter Logic
FPGA
Logic
Array
TX Phase
Compensation
FIFO
BIST
Incremental
Verify
Byte
Serializer
RX Phase
Compen-
sation
FIFO
Byte
Ordering
8B/10B
20 ^Encoder
Byte
De-
serializer
8B/10B
Decoder
Rate
Match
FIFO
Serializer
BIST
PRBS
Verify
Deskew
FIFO
Word
Aligner
Reverse
Serial
Pre-CDR
Loopback
De-
serializer
Clock
Recovery
Unit
Receiver Digital Logic
PCI Express PIPE Reverse Parallel Loopback
This loopback mode, available only in PIPE mode, can be dynamically
enabled by the tx_detectrxloopback port of the PIPE interface.
Figure 2–28 shows the datapath for this mode.
Figure 2–28. Stratix II GX Block in PCI Express PIPE Reverse Parallel Loopback Mode
Transmitter Digital Logic
BIST
Incremental
Generator
BIST
PRBS
Generator
Analog Receiver and
Transmitter Logic
FPGA
Logic
Array
TX Phase
Compensation
FIFO
BIST
Incremental
Verify
Byte
Serializer
RX Phase
Compen-
sation
FIFO
Byte
Ordering
8B/10B
Encoder
20
PCI Express PIPE
Reverse Parallel
Loopback
Byte
De-
serializer
8B/10B
Decoder
Rate
Match
FIFO
Serializer
BIST
PRBS
Verify
Deskew
FIFO
Word
Aligner
De-
serializer
Clock
Recovery
Unit
Receiver Digital Logic
2–34
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007