EP2SGX60CF780C4N Datasheet, PDF (132/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

I/O Structure
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These dedicated circuits combined, with enhanced PLL clocking and
phase-shift ability, provide a complete hardware solution for interfacing
to high-speed memory.
For more information on external memory interfaces, refer to the
External Memory Interfaces in Stratix II & Stratix II GX Devices chapter in
volume 2 of the Stratix II GX Device Handbook.
Programmable Drive Strength
The output buffer for each Stratix II GX device I/O pin has a
programmable drive strength control for certain I/O standards. The
LVTTL, LVCMOS, SSTL, and HSTL standards have several levels of drive
strength that you can control. The default setting used in the Quartus II
software is the maximum current strength setting that is used to achieve
maximum I/O performance. For all I/O standards, the minimum setting
is the lowest drive strength that guarantees the I_OH/I_OL of the standard.
Using minimum settings provides signal slew rate control to reduce
system noise and signal overshoot.
2–124
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007