EP2SGX60CF780C4N Datasheet, PDF (295/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Table 4–104. Maximum DCD for DDIO Output on Row I/O Pins With PLL in the
Clock Path
Maximum DCD (ps) for ^{Stratix II GX Devices (PLL Output Feeding}
Row DDIO Output I/O
DDIO)
Unit
Standard
-3 Device
-4 and -5 Device
3.3-V LVTTL
110
105
ps
3.3-V LVCMOS
65
75
ps
2.5V
75
90
ps
1.8V
85
100
ps
1.5-V LVCMOS
105
100
ps
SSTL-2 Class I
65
75
ps
SSTL-2 Class II
60
70
ps
SSTL-18 Class I
50
65
ps
1.8-V HSTL Class I
50
70
ps
1.5-V HSTL Class I
55
70
ps
LVDS
180
180
ps
Table 4–105. Maximum DCD for DDIO Output on Column I/O Pins With PLL in
the Clock Path (Part 1 of 2)
Maximum DCD (ps) for ^{Stratix II GX Devices (PLL Output Feeding}
Column DDIO Output I/O
DDIO)
Unit
Standard
-3 Device
-4 and -5 Device
3.3-V LVTTL
145
160
ps
3.3-V LVCMOS
100
110
ps
2.5V
85
95
ps
1.8V
85
100
ps
1.5-V LVCMOS
140
155
ps
SSTL-2 Class I
65
75
ps
SSTL-2 Class II
60
70
ps
SSTL-18 Class I
50
65
ps
SSTL-18 Class II
70
80
ps
1.8-V HSTL Class I
60
70
ps
1.8-V HSTL Class II
60
70
ps
1.5-V HSTL Class I
55
70
ps
1.5-V HSTL Class II
85
100
ps