EP2SGX60CF780C4N Datasheet, PDF (136/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

I/O Structure
Table 2–33. Stratix II GX Supported I/O Standards
I/O Standard
SSTL-2 class I and II
Input Reference Output Supply Board Termination
Type
Voltage (V_REF) (V) Voltage (V_CCIO) (V) Voltage (V_TT) (V)
Voltage-referenced
1.25
2.5
1.25
Notes to Table 2–33:
(1) This I/O standard is only available on input and output column clock pins.
(2) This I/O standard is only available on input clock pins and DQS pins in I/O banks 3, 4, 7, and 8, and output clock
pins in I/O banks 9,10, 11, and 12.
(3) V_CCIO is 3.3 V when using this I/O standard in input and output column clock pins (in I/O banks 3, 4, 7, 8, 9, 10,
11, and 12).
(4) 1.2-V HSTL is only supported in I/O banks 4, 7, and 8.
f
For more information on I/O standards supported by Stratix II GX I/O
banks, refer to the Selectable I/O Standards in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II GX Device Handbook.
Stratix II GX devices contain six I/O banks and four enhanced PLL
external clock output banks, as shown in Figure 2–87. The two I/O banks
on the left of the device contain circuitry to support source-synchronous,
high-speed differential I/O for LVDS inputs and outputs. These banks
support all Stratix II GX I/O standards except PCI or PCI-X I/O pins, and
SSTL-18 class II and HSTL outputs. The top and bottom I/O banks
support all single-ended I/O standards. Additionally, enhanced PLL
external clock output banks allow clock output capabilities such as
differential support for SSTL and HSTL.
2–128
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007