EP2SGX60CF780C4N Datasheet, PDF (25/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Stratix II GX Architecture
1 The Stratix II GX receivers also have adaptive equalization
capability that adjusts the equalization levels to compensate for
changing link characteristics. The adaptive equalization can be
powered down dynamically after it selects the appropriate
equalization levels.
The receiver equalization circuit is comprised of a programmable
amplifier. Each stage is a peaking equalizer with a different center
frequency and programmable gain. This allows varying amounts of gain
to be applied, depending on the overall frequency response of the channel
loss. Channel loss is defined as the summation of all losses through the
PCB traces, vias, connectors, and cables present in the physical link.
Figure 2–15 shows the frequency response for the 16 programmable
settings allowed by the Quartus II software for Stratix II GX devices.
Figure 2–15. Frequency Response
High
Medium
Low
Bypass EQ
Receiver PLL and CRU
Each transceiver block has four receiver PLLs, lock detectors, signal
detectors, run length checkers, and CRU units, each of which is dedicated
to a receive channel. If the receive channel associated with a particular
receiver PLL or CRU is not used, the receiver PLL and CRU are powered
down for the channel. Figure 2–16 shows the receiver PLL and CRU
circuits.
Altera Corporation
October 2007
2–17
Stratix II GX Device Handbook, Volume 1