EP2SGX60CF780C4N Datasheet, PDF (139/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Stratix II GX Architecture
Table 2–34. On-Chip Termination Support by I/O Banks (Part 2 of 2)
On-Chip Termination Support
I/O Standard Support
Top and Bottom Banks
(3, 4, 7, 8)
3.3-V LVTTL
v
3.3-V LVCMOS
v
2.5-V LVTTL
v
2.5-V LVCMOS
v
1.8-V LVTTL
v
1.8-V LVCMOS
v
Series termination with
1.5-V LVTTL
v
calibration
1.5-V LVCMOS
v
SSTL-2 class I and II
v
SSTL-18 class I and II
v
1.8-V HSTL class I
v
1.8-V HSTL class II
v
1.5-V HSTL class I
v
1.2-V HSTL
v
LVDS
—
Differential termination (1)
HyperTransport technology
—
Left Bank (1, 2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
v
v
Note to Table 2–34:
(1) Clock pins CLK1 and CLK3, and pins FPLL[7..8]CLK do not support differential on-chip termination. Clock pins
CLK0 and CLK2, do support differential on-chip termination. Clock pins in the top and bottom banks (CLK[4..7,
12..15]) do not support differential on-chip termination.
f
Differential On-Chip Termination
Stratix II GX devices support internal differential termination with a
nominal resistance value of 100 for LVDS input receiver buffers. LVPECL
input signals (supported on clock pins only) require an external
termination resistor. Differential on-chip termination is supported across
the full range of supported differential data rates, as shown in the
High-Speed I/O Specifications section of the DC & Switching Characteristics
chapter in volume 1 of the Stratix II GX Device Handbook.
For more information on differential on-chip termination, refer to the
High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II GX Device Handbook.
Altera Corporation
October 2007
2–131
Stratix II GX Device Handbook, Volume 1