EP2SGX60CF780C4N Datasheet, PDF (252/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Table 4–79. Clock Network Specifications (Part 2 of 2)
Name
Clock skew adder
EP2SGX130 (1)
Description
Inter-clock network, same side
Inter-clock network, entire chip
Min
Typ
Max Unit
±63
ps
±125
ps
(1) This is in addition to intra-clock network skew, which is modeled in the Quartus II software.
IOE Programmable Delay
See Tables 4–80 and 4–81 for IOE programmable delay.
Table 4–80. Stratix II GX IOE Programmable Delay on Column Pins Note (1)
Parameter
Paths
Affected
Available
Settings
Minimum
Timing
Min Max
-3 Speed
Grade (2)
Min Max
-3 Speed
Grade (3)
-4 Speed Grade
-5 Speed
Grade
Min Max Min Max Min Max
Unit
Offset Offset Offset Offset Offset Offset Offset Offset Offset Offset
Input
Pad to
8
delay from I/O
pin to
dataout
internal to core
cells
0 1781 0 2881 0 3025 0 3217 0 3,860 ps
Input
Pad to
64
delay from I/O input
pin to
register
input
register
0 2053 0 3275 0 3439 0 3657 0 4388 ps
Delay
I/O
2
from
output
output
register
register to to pad
output pin
0 332 0 500 0 525 0 559 0 670 ps
Output
t_XZ, t_ZX
2
0 320 0 483 0 507 0 539 0 647 ps
enable pin
delay
(1) The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the latest
version of the Quartus II software.
(2) This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
(3) This column refers to –3 speed grades for EP2SGX130 devices.