EP2SGX60CF780C4N Datasheet, PDF (86/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

TriMatrix Memory
Figure 2–55. M-RAM Block LAB Row Interface Note (1)
Row Unit Interface Allows LAB
Rows to Drive Port A Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
Row Unit Interface Allows LAB
Rows to Drive Port B Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
L0
L1
L2 _{Port A}
L3
L4
L5
M-RAM Block
R0
R1
Port B ^R2
R3
R4
R5
LAB Interface
Blocks
LABs in Row
M-RAM Boundary
Note to Figure 2–55:
(1) Only R24 and C16 interconnects cross the M-RAM block boundaries.
LABs in Row
M-RAM Boundary
2–78
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007