EP2SGX60CF780C4N Datasheet, PDF (311/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Table 4–118. Document Revision History (Part 5 of 5)
Date and
Document
Version
Changes Made
April 2006, v3.0
February 2006,
v2.1
● Updated Table 6–3.
● Updated Table 6–5.
● Updated Table 6–7.
● Added Table 6–42.
● Updated “Internal Timing Parameters” section
(Tables 6–43 through 6–48).
● Updated “Stratix II GX Clock Timing
Parameters” section (Tables 6–49 through
6–65).
● Updated “IOE Programmable Delay” section
(Tables 6–67 and 6–68)
● Updated “I/O Delays” section (Tables 6–71
through 6–74.
● Updated “Maximum Input & Output Clock Toggle
Rate” section. Replaced tables 6-73 and 6-74
with Tables 6–75 through 6–83. Input and output
clock rates for row, column, and dedicated clock
pins are now in separate tables.
● Updated Tables 6–4 and 6–5.
● Updated Tables 6–49 through 6–65 (removed
column designations for industrial/commercial
and removed industrial numbers).
December 2005, Updated timing numbers.
v2.0
October 2005
v1.1
October 2005
v1.0
● Updated Table 6–7.
● Updated Table 6–38.
● Updated 3.3-V PCML information and notes to
Tables 6–73 through 6–76.
● Minor textual changes throughout the
document.
Added chapter to the Stratix II GX Device
Handbook.
Summary of Changes