EP2SGX60CF780C4N Datasheet, PDF (241/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

DC and Switching Characteristics
Table 4–58. DSP Block Internal Timing Microparameters (Part 2 of 2)
Symbol
Parameter
t_INREG2PIPE9
Input register to
DSP block pipeline
register in 9 × 9-bit
mode
t_INREG2PIPE18
Input register to
DSP block pipeline
register in 18 × 18-
bit mode
t_INREG2PIPE36
Input register to
DSP block pipeline
register in 36 × 36-
bit mode
t_{PIPE2OUTREG2ADD} DSP block pipeline
register to output
register delay in
two-multipliers
adder mode
t_{PIPE2OUTREG4ADD} DSP block pipeline
register to output
register delay in
four-multipliers
adder mode
t_PD9
Combinational input
to output delay for
9×9
t_PD18
Combinational input
to output delay for
18 × 18
t_PD36
Combinational input
to output delay for
36 × 36
t_CLR
Minimum clear pulse
width
t_CLKL
Minimum clock low
time
t_CLKH
Minimum clock high
time
-3 Speed
Grade (1)
Min Max
1312 2030
1302 2010
1302 2010
924 1450
1134 1850
2100 2880
2110 2990
2939 4450
2212
1190
1190
-3 Speed
Grade (2)
Min Max
1312 2131
1302 2110
1302 2110
924 1522
1134 1942
2100 3024
2110 3139
2939 4672
2322
1249
1249
-4 Speed
Grade
Min Max
1312 2266
1302 2244
1302 2244
924 1618
1134 2065
2100 3214
2110 3337
2939 4967
2469
1328
1328
-5 Speed
Grade _Unit
Min Max
1312 2720 ps
1302 2693 ps
1302 2693 ps
924 1943 ps
1134 2479 ps
2100 3859 ps
2110 4006 ps
2939 5962 ps
2964
ps
1594
ps
1594
ps
(1) This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
(2) This column refers to –3 speed grades for EP2SGX130 devices.
Altera Corporation
June 2009
4–71
Stratix II GX Device Handbook, Volume 1