EP2SGX60CF780C4N Datasheet, PDF (137/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Stratix II GX Architecture
Figure 2–87. Stratix II GX I/O Banks Notes (1), (2)
DQS ×8
DQS ×8
DQS ×8
DQS ×8
PLL7 VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3
Bank 3
PLL11
Bank 11
PLL5
Bank 9
DQS ×8 DQS ×8 DQS ×8 DQS ×8 DQS ×8
VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4
Bank 4
This I/O bank supports LVDS
and LVPECL standards
for input clock operations. Differential HSTL
and differential SSTL standards
are supported for both input
and output operations. (3)
I/O Banks 3, 4, 9, and 11 support all single-ended
I/O standards for both input and output operations.
All differential I/O standards are supported for both
input and output operations at I/O banks 9 and 11.
This I/O bank supports LVDS
and LVPECL standards for input clock
operation. Differential HSTL and
differential SSTL standards are
supported for both input and output
operations. (3)
I/O banks 1 & 2 support LVTTL, LVCMOS,
2.5 V, 1.8 V, 1.5 V, SSTL-2, SSTL-18 class I,
LVDS, pseudo-differential SSTL-2 and pseudo-differential
PLL1
SSTL-18 class I standards for both input and output
operations. HSTL-18 class II, SSTL-18 class II,
PLL2
pseudo-differential HSTL and pseudo-differential
SSTL-18 class II standards are only supported for
input operations. (4)
I/O banks 7, 8, 10 and 12 support all single-ended I/O
standards for both input and output operations. All differential
I/O standards are supported for both input and output operations
at I/O banks 10 and 12.
This I/O bank supports LVDS
This I/O bank supports LVDS
and LVPECL standards for input clock operation.
and LVPECL standards for input clock
Differential HSTL and differential
operation. Differential HSTL and differential
SSTL standards are supported
SSTL standards are supported
for both input and output operations. (3)
for both input and output operations. (3)
Transmitter: Bank 13
Receiver: Bank 13
REFCLK: Bank 13
Transmitter: Bank 14
Receiver: Bank 14
REFCLK: Bank 14
Transmitter: Bank 15
Receiver: Bank 15
REFCLK: Bank 15
Bank 8
PLL8 VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8
DQS ×8
DQS ×8
DQS ×8
DQS ×8
Bank 12
PLL12
Bank 10
PLL6
Bank 7
VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7
DQS ×8 DQS ×8 DQS ×8 DQS ×8 DQS ×8
Notes to Figure 2–87:
(1) Figure 2–87 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical
representation only.
(2) Depending on the size of the device, different device members have different numbers of V_REF groups. Refer to the
pin list and the Quartus II software for exact locations.
(3) Banks 9 through 12 are enhanced PLL external clock output banks.
(4) Horizontal I/O banks feature SERDES and DPA circuitry for high-speed differential I/O standards. See the
High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II
Device Handbook 2 for more information on differential I/O standards.
Each I/O bank has its own VCCIO pins. A single device can support
1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different
V_CCIO level independently. Each bank also has dedicated VREF pins to
support the voltage-referenced standards (such as SSTL-2).
Each I/O bank can support multiple standards with the same V_CCIO for
input and output pins. Each bank can support one V_REF voltage level. For
example, when V_CCIO is 3.3 V, a bank can support LVTTL, LVCMOS, and
3.3-V PCI for inputs and outputs.
Altera Corporation
October 2007
2–129
Stratix II GX Device Handbook, Volume 1