EP2SGX60CF780C4N Datasheet, PDF (119/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Stratix II GX Architecture
■ Open-drain outputs
■ DQ and DQS I/O pins
■ Double data rate (DDR) registers
The IOE in Stratix II GX devices contains a bidirectional I/O buffer, six
registers, and a latch for a complete embedded bidirectional single data
rate or DDR transfer. Figure 2–76 shows the Stratix II GX IOE structure.
The IOE contains two input registers (plus a latch), two output registers,
and two output enable registers. You can use both input registers and the
latch to capture DDR input and both output registers to drive DDR
outputs. Additionally, you can use the output enable (OE) register for fast
clock-to-output enable timing. The negative edge-clocked OE register is
used for DDR SDRAM interfacing. The Quartus II software automatically
duplicates a single OE register that controls multiple output or
bidirectional pins.
Altera Corporation
October 2007
2–111
Stratix II GX Device Handbook, Volume 1