EP2SGX60CF780C4N Datasheet, PDF (251/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

DC and Switching Characteristics
Table 4–77. EP2SGX130 Column Pins Regional Clock Timing Parameters
Parameter
t_{C I N}
t_{C O U T}
t_{P L L C I N}
t_{P L L C O U T}
Fast Corner
Industrial Commercial
1.815
1.650
0.116
-0.049
1.834
1.669
0.134
-0.031
-3 Speed
Grade
3.218
3.218
0.349
0.361
-4 Speed
Grade
3.417
3.417
0.364
0.378
-5 Speed
Grade
4.087
4.087
0.426
0.444
Units
ns
ns
ns
ns
Table 4–78. EP2SGX130 Row Pins Regional Clock Timing Parameters
Parameter
t_{C I N}
t_{C O U T}
t_{P L L C I N}
t_{P L L C O U T}
Fast Corner
Industrial Commercial
1.544
1.549
-0.149
-0.144
1.560
1.565
-0.132
-0.127
-3 Speed
Grade
3.195
3.195
0.34
0.342
-4 Speed
Grade
3.395
3.395
0.356
0.356
-5 Speed
Grade
4.060
4.060
0.417
0.417
Units
ns
ns
ns
ns
Clock Network Skew Adders
The Quartus II software models skew within dedicated clock networks
such as global and regional clocks. Therefore, the intra-clock network
skew adder is not specified. Table 4–79 specifies the intra-clock skew
between any two clock networks driving any registers in the Stratix II GX
device.
Table 4–79. Clock Network Specifications (Part 1 of 2)
Name
Clock skew adder
EP2SGX30 (1)
Clock skew adder
EP2SGX60 (1)
Clock skew adder
EP2SGX90 (1)
Description
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Min
Typ
Max Unit
±50
ps
±100
ps
±50
ps
±100
ps
±55
ps
±110
ps
Altera Corporation
June 2009
4–81
Stratix II GX Device Handbook, Volume 1