EP2SGX60CF780C4N Datasheet, PDF (146/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

High-Speed Differential I/O with DPA Support
Table 2–41. EP2SGX130 Device Differential Channels Note (1)
Package
Transmitter/Receiver
Total
Channels
Transmitter
71
1508-pin FineLine BGA
Receiver
73
Center Fast PLLs
PLL1
PLL2
37
41
37
41
Corner Fast PLLs
PLL7
PLL8
37
41
37
41
Note to Tables 2–38 through 2–41:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
Therefore, the total number of channels is not the addition of the number
of channels accessible by PLLs 1 and 2 with the number of channels
accessible by PLLs 7 and 8.
Dedicated Circuitry with DPA Support
Stratix II GX devices support source-synchronous interfacing with LVDS
signaling at up to 1 Gbps. Stratix II GX devices can transmit or receive
serial channels along with a low-speed or high-speed clock.
The receiving device PLL multiplies the clock by an integer factor W = 1
through 32. The SERDES factor J determines the parallel data width to
deserialize from receivers or to serialize for transmitters. The SERDES
factor J can be set to 4, 5, 6, 7, 8, 9, or 10 and does not have to equal the PLL
clock-multiplication W value. A design using the dynamic phase aligner
also supports all of these J factor values. For a J factor of 1, the
Stratix II GX device bypasses the SERDES block. For a J factor of 2, the
Stratix II GX device bypasses the SERDES block, and the DDR input and
output registers are used in the IOE. Figure 2–88 shows the block diagram
of the Stratix II GX transmitter channel.
2–138
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007