EP2SGX60CF780C4N Datasheet, PDF (142/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

I/O Structure
Table 2–35 summarizes Stratix II GX MultiVolt I/O support.
Table 2–35. Stratix II GX MultiVolt I/O Support Note (1)
Input Signal (V)
Output Signal (V)
V_CCIO (V)
1.2 1.5 1.8 2.5 3.3 1.2 1.5 1.8 2.5 3.3 5.0
1.2
(4) v (2) v (2) v (2) v (2) v (4) — —
— ——
1.5
(4) v
v v (2) v (2) v (3) v —
— ——
1.8
(4) v
v v (2) v (2) v (3) v (3) v
— ——
2.5
(4) —
—
v
v v (3) v (3) v (3) v — —
3.3
(4) —
—
v
v v (3) v (3) v (3) v (3) v v
Notes to Table 2–35:
(1) To drive inputs higher than V_CCIO but less than 4.0 V, disable the PCI clamping diode and select
the Allow LVTTL and LVCMOS input levels to overdrive input buffer option in the Quartus II
software.
(2) The pin current may be slightly higher than the default value. You must verify that the driving
device’s V_{O L} maximum and V_{O H} minimum voltages do not violate the applicable Stratix II GX
V_{I L} maximum and V_{I H} minimum voltage specifications.
(3) Although V_CCIO specifies the voltage necessary for the Stratix II GX device to drive out, a
receiving device powered at a different level can still interface with the Stratix II GX device if it
has inputs that tolerate the V_CCIO value.
(4) Stratix II GX devices support 1.2-V HSTL. They do not support 1.2-V LVTTL and 1.2-V LVCMOS.
The TDO and nCEO pins are powered by V_CCIO of the bank that they reside.
TDO is in I/O bank 4 and nCEO is in I/O bank 7. Ideally, the V_CC supplies
for the I/O buffers of any two connected pins are at the same voltage
level. This may not always be possible depending on the V_CCIO level of
TDO and nCEO pins on master devices and the configuration voltage level
chosen by V_CCSEL on slave devices. Master and slave devices can be in any
position in the chain. Master indicates that it is driving out TDO or nCEO
to a slave device. For multi-device passive configuration schemes, the
nCEO pin of the master device drives the nCE pin of the slave device. The
VCCSEL pin on the slave device selects which input buffer is used for nCE.
When V_CCSEL is logic high, it selects the 1.8-V/1.5-V buffer powered by
V_CCIO. When V_CCSEL is logic low, it selects the 3.3-V/2.5-V input buffer
powered by V_CCPD. The ideal case is to have the V_CCIO of the nCEO bank
in a master device match the V_CCSEL settings for the nCE input buffer of
the slave device it is connected to, but that may not be possible depending
on the application.
2–134
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007