EP2SGX60CF780C4N Datasheet, PDF (207/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

DC and Switching Characteristics
Table 4–20. Recommended Input Clock Jitter (Part 2 of 2)
Mode
SONET/SDH
OC-48
SONET/SDH
OC-12
Reference
Clock (MHz)
77.76
155.52
311.04
622.08
62.2
311
77.76
155.52
622.08
Vectron
LVPECL XO
Type/Model
VCC6-Q/R
VCC6-Q/R
VCC6-Q
VCC6-Q
VCC6-Q/R
VCC6-Q
VCC6-Q/R
VCC6-Q/R
VCC6-Q
Frequency
Range (MHz)
RMS Jitter
(12 kHz to 20
MHz) (ps)
10 to 270
0.3
10 to 270
0.3
270 to 800
2
270 to 800
2
10 to 270
0.3
270 to 800
2
10 to 270
0.3
10 to 270
0.3
270 to 800
2
Period Jitter
(Peak to
Peak) (ps)
23
23
30
30
23
30
23
23
30
Phase Noise
at 1 MHz
(dB c/Hz)
-149.5476
-149.1903
Not available
Not available
-149.6289
Not available
-149.5476
-149.1903
Not available
Tables 4–21 and 4–22 show the transmitter and receiver PCS latency for
each mode, respectively.
Table 4–21. PCS Latency (Part 1 of 2) Note (1)
Transmitter PCS Latency
Functional Mode
Configuration
TX PIPE
TX
Phase
Comp
FIFO
Byte TX State
Serializer Machine
XAUI
-
2-3
1
0.5
PIPE
×1, ×4, ×8
1
3-4
1
-
8-bit channel
width
×1, ×4, ×8
1
3-4
1
-
16-bit channel
width
GIGE
-
2-3
1
-
OC-12
-
2-3
1
-
SONET/SDH
OC-48
-
2-3
1
-
OC-96
-
2-3
1
-
(OIF) CEI PHY
-
2-3
1
-
CPRI (3)
614 Mbps,
-
2
1
-
1.228 Gbps
2.456 Gbps
-
2-3
1
-
8B/10B
Encoder
0.5
1
0.5
1
1
0.5
0.5
0.5
1
1
Sum (2)
4-5
6-7
6-7
4-5
4-5
4-5
4-5
4-5
4
4-5
Altera Corporation
June 2009
4–37
Stratix II GX Device Handbook, Volume 1