EP2SGX60CF780C4N Datasheet, PDF (305/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Figure 4–14. Stratix II GX JTAG Waveforms.
TMS
TDI
TCK
TDO
Signal
to be
Captured
Signal
to be
Driven
t _JCP
t _JCH
t _JCL
t _JPSU
t_JPZX
t_JSSU
t_JPCO
t_JSH
t_JSZX
t_JSCO
t _JPH
t _JPXZ
t_JSXZ
Table 4–117 shows the JTAG timing parameters and values for
Stratix II GX devices.
Table 4–117. Stratix II GX JTAG Timing Parameters and Values
Symbol
Parameter
t_JCP
t_JCH
t_JCL
t_JPSU
t_JPH
t_JPCO
t_JPZX
t_JPXZ
t_JSSU
t_JSH
t_JSCO
t_JSZX
t_JSXZ
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
Min Max Unit
30
ns
12
ns
12
ns
4
ns
5
ns
9 ns
9 ns
9 ns
4
ns
5
ns
12 ns
12 ns
12 ns