EP2SGX60CF780C4N Datasheet, PDF (239/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

DC and Switching Characteristics
Internal Timing Parameters
Refer to Tables 4–56 through 4–61 for internal timing parameters.
Table 4–56. LE_FF Internal Timing Microparameters
Symbol
Parameter
-3 Speed
Grade (1)
Min Max
-3 Speed
Grade (2)
-4 Speed Grade
-5 Speed
Grade
Unit
Min Max Min Max Min Max
t_SU
LE register setup time
90
95
101
before clock
121
ps
t_H
LE register hold time after 149
157
167
clock
200
ps
t_CO
LE register
clock-to-output delay
62 94 62 99
62
105
62 127 ps
t_CLR
Minimum clear pulse
204
214
227
width
273
ps
t_PRE
Minimum preset pulse
204
214
227
width
273
ps
t_CLKL
Minimum clock low time 612
642
683
820
ps
t_CLKH
Minimum clock high time 612
642
683
820
ps
t_{L U T}
170 378 170 397 170 422 170 507
t_{A D D E R}
372 619 372 650 372 691 372 829
Notes to Table 4–56:
(1) This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
(2) This column refers to –3 speed grades for EP2SGX130 devices.
Table 4–57. IOE Internal Timing Microparameters (Part 1 of 2)
Symbol
t_SU
t_H
t_CO
Parameter
IOE input and output
register setup time
before clock
IOE input and output
register hold time after
clock
IOE input and output
register clock-to-output
delay
-3 Speed
Grade (1)
Min Max
122
72
101 169
-3 Speed
Grade (2)
Min Max
128
75
101 177
-4 Speed
Grade
Min Max
136
80
101 188
-5 Speed
Grade _Unit
Min Max
163
ps
96
ps
101 226 ps
Altera Corporation
June 2009
4–69
Stratix II GX Device Handbook, Volume 1