EP2SGX60CF780C4N Datasheet, PDF (49/316 Pages) Altera Corporation – Support for numerous single-ended and differential I/O standards

Stratix II GX Architecture
.
Table 2–15. Available Clocking Connections for Transceivers in 2SGX130G
Region
Region0
8 LRIO clock
Region1
8 LRIO clock
Region2
8 LRIO clock
Region3
8 LRIO clock
Clock Resource
Global
Clock
v
Regional
Clock
RCLK 20-27
Bank 13
8 Clock I/O
v
v
RCLK 20-27
v
RCLK 12-19
v
RCLK 12-19
Bank 14
8 Clock I/O
v
Transceiver
Bank 15
Bank 16
8 clock I/O 8 Clock I/O
v
v
v
Bank 17
8 Clock I/O
v
Other Transceiver Features
Other important features of the Stratix II GX transceivers are the power
down and reset capabilities, external voltage reference and bias circuitry,
and hot swapping.
Calibration Block
The Stratix II GX device uses the calibration block to calibrate the on-chip
termination for the PLLs and their associated output buffers and the
terminating resistors on the transceivers. The calibration block counters
the effects of process, voltage, and temperature (PVT). The calibration
block references a derived voltage across an external reference resistor to
calibrate the on-chip termination resistors on the Stratix II GX device. The
calibration block can be powered down. However, powering down the
calibration block during operations may yield transmit and receive data
errors.
Dynamic Reconfiguration
This feature allows you to dynamically reconfigure the PMA portion and
the channel parameters, such as data rate and functional mode, of the
Stratix II GX transceiver. The PMA reconfiguration allows you to quickly
optimize the settings for the transceiver’s PMA to achieve the intended
bit error rate (BER).
Altera Corporation
October 2007
2–41
Stratix II GX Device Handbook, Volume 1