Z80189 Datasheet, PDF (99/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
PARALLEL PORTS REGISTERS (Continued)
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
765 43210
XXXXXXXX
7 65 4 321 0
XX1 1 1 11 1
PA Data Register
Figure 125. PA Data Register
(Z180 MPU Address XXEEH)
When the Z180 MPU writes to the PA Data Register, the
data is stored in the internal buffer. Any bits that are output
are then sent on to the output buffers.
When the Z180 MPU reads the PA Data Register, the data
on the external pins is returned.
7 65 4 321 0
1 11 1 1 11 1
PB Data Direction Register
0 = Output
1 = Input
Figure 126. PB Data Direction Register
(Z180 MPU Address XXE4H)
The data direction register determines which are inputs
and outputs in the PB Data Register. When a bit is set to a
one, the corresponding bit in the PB Data Register is an
input. If the bit is zero, then the corresponding bit is an
output.
PB Data Direction Register
0 = Output
1 = Input
Reserved
Figure 128. PC Data Direction Register
(Z180 MPU Address XXDDH)
The data direction register determines which are inputs
and outputs in the PB Data Register. When a bit is set to a
one, the corresponding bit in the PB Data Register is an
input. If the bit is zero, then the corresponding bit is an
output.
765 43210
X XX X X XX X
/INT2, /INT1 Read Ext Data
Write B7=1 Clears /INT2 Edge
Write B6=1 Clears /INT1 Edge
PC Data Register
Figure 129. PC, Port C, Data Register
(Z180 MPU Address XXDEH)
When the Z180 MPU writes to the PC Data Register, the
data is stored in the internal buffer. Any bits that are output
are then sent on to the output buffers.
765 43210
X XX XX XXX
When the Z180 MPU reads the PC Data Register, the data
on the external pins is returned.
PB Data Register
Figure 127. PB Data Register
(Z180 MPU Address XXE5H)
When the Z180 MPU writes to the PB Data Register, the
data is stored in the internal buffer. Any bits that are output
are then sent on to the output buffers.
Bits 7 and 6 serve the special function of reading the value
of the external /INT2 and /INT1 lines. When operating either
/INT2 or /INT1 in edge detection mode, the edge detect
latch is reset by writing a '1' to bit 7 or 6 respectively.
Writing a '0' has no effect. These latches should be reset
at the end of an /INT1 or /INT2 interrupts service routine
when using edge-triggered interrupt routine.
When the Z180 MPU reads the PB Data Register, the data
on the external pins is returned.
DS971890301
99