Z80189 Datasheet, PDF (9/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
TIMING DIAGRAMS (Continued)
T1
0
I/O Read Cycle
T2
TW
T3
I/O Write Cycle
T1
T2
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
TW
T3
Address
28
29
28
29
/IROQ
9
/RD
/WR
13
22
25
Figure 7. CPU Timing
Ø
/DREQi
(At level
sense)
/DREQi
(At edge
sence)
/TENDi
ST
CPU or DMA Read/Write Cycle (Only DMA Write Cycle for /TENDi)
T1
T2
Tw
T3
T1
45
46 ^[1]
45
45 ^[2]
47
[3]
17
18
[4]
48
DMA Control Signals
[1] tDRQS and tDRQH are specified for the rising edge of clock followed by T3.
[2] tDRQS and tDRQH are specified for the rising edge of clock.
[3] DMA cycle starts.
[4] CPU cycle starts.
Figure 8. DMA Control Signals
DS971890301
9