Z80189 Datasheet, PDF (56/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
DMA REGISTER DESCRIPTION
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Bit 7. This bit should be set to 1 only when both DMA
channels are set to take their requests from the same
device. If this bit is 1 (it resets to 0), the TEND output of DMA
channel 0 sets a flip-flop, so that thereafter the device’s
request is visible to channel 1, but is not visible to channel
0. The internal TEND signal of channel 1 clears the FF, so
that thereafter, the device’s request is visible to channel 0,
but not visible to channel 1.
If DMA requests are from differing sources, DMA channel
0 request will be forced onto DMA channel 1 once TEND
output of DMA channel 0 sets the flop-flop to alternate.
Bit 6. When both DMA channels are programmed to take
their requests from the same device, this bit (FF mentioned
in the previous paragraph) controls which channel the
device’s request is presented to: 0 = DMA 0, 1 = channel
1. When bit 7 is 1, this bit is automatically toggled by the
channel end output of the channels, as described above.
Bits 5-3. Reserved and should be programmed as 0.
Bits 2-0. With “DIM1”, bit 1 of DCNTL, these bits control
which request is presented to DMA channel 1, as follows:
DIM1 IAR18-16 Request Routed to DMA Channel 1
0
000
0
001
0
010
0
011
0
10X
0
1X0
0
111
/DREQ1
ASCI0 Tx
ASCI1 Tx
ext CKA0//DREQ0
Reserved, do not program.
Reserved, do not program.
Reserved, do not program
1
000
1
001
1
010
1
011
1
10X
1
1X0
1
111
ext /DREQ1
ASCI0 Rx
ASCI1 Rx
ext CKA0//DREQ0
Reserved, do not program.
Reserved, do not program.
Reserved, do not program
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DS971890301