Z80189 Datasheet, PDF (27/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PIN DESCRIPTION
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
CPU Signals
A19-A0. Address Bus (Input/Output, active High, tri-state).
A0-A19 form a 20-bit address bus. The Address Bus
provides the address for memory data bus exchanges, up
to 1 Mbyte, and I/O data bus exchanges, up to 64K. The
address bus enters a high impedance state during reset
and external bus acknowledge cycles, as well as during
SLEEP and HALT states. This bus is an input when the
external bus master is accessing the on-chip peripherals.
/HALT. Halt/Sleep Status (Output, active Low). This output
is asserted after the CPU has executed either the HALT or
SLP instruction, and is waiting for either non-maskable or
maskable interrupt before operation can resume. It is also
used with the /M1 and ST signals to decode status of the
CPU machine cycle. On exit of Halt/Sleep, the first instruc-
tion fetch is delayed 16 clock cycles after the /HALT pin
goes high.
D7-D0. Data Bus (Bidirectional, active High, tri-state). D0-
D7 constitute an 8-bit bidirectional data bus, used for the
transfer of information to and from I/O and memory de-
vices. The data bus enters the high impedance state
during reset and external bus acknowledge cycles, as well
as during SLEEP and HALT states.
/RD. Read (Input/Output, active Low, tri-state). /RD indi-
cates that the CPU wants to read data from memory or an
I/O device. The addressed I/O or memory device should
use this signal to gate data onto the CPU data bus.
/WR. Write (Output, active Low, tri-state). /WR indicates
that the CPU data bus holds valid data to be stored at the
addressed I/O or memory location.
/IORQ. I/O Request (Input/Output, active Low, tri-state).
/IORQ indicates that the address bus contains a valid I/O
address for an I/O read or I/O write operation. /IORQ is also
generated, along with /M1, during the acknowledgment of
the /INT0 input signal to indicate that an interrupt response
vector can be placed onto the data bus.
/M1. Machine Cycle 1 (Input/Output, active Low). Together
with /MREQ, /M1 indicates that the current cycle is the
opcode fetch cycle of an instruction execution. Together
with /IORQ, /M1 indicates that the current cycle is for an
interrupt acknowledge. It is also used with the /HALT and
ST signal to decode status of the CPU machine cycle.
/MREQ. Memory Request (Input/Output, active Low, tri-
state). /MREQ indicates that the address bus holds a valid
address for a memory read or memory write operation.
/WAIT. (Input, active Low). /WAIT indicates to the MPU that
the addressed memory or I/O devices are not ready for a
data transfer. This input is used to induce additional clock
cycles into the current machine cycle. The /WAIT input is
sampled on the falling edge of t2 (and subsequent wait
states). If the input is sampled low, then additional wait
states are inserted until the /WAIT input is sampled high, at
which time execution will continue.
/BUSACK. Bus Acknowledge (Output, active Low
tri-state). /BUSACK indicates to the requesting device, the
MPU address and data bus, and some control signals,
have entered their high-impedance state.
/BUSREQ. Bus Request (Input, active Low). This input is
used by external devices (such as DMA controllers) to
request access to the system bus. This request has a
higher priority than /NMI and is always recognized at the
end of the current machine cycle. This signal will stop the
CPU from executing further instructions and places the
address and data buses, and other control signals, into the
high impedance state.
/NMI. Non-maskable interrupt (Input, negative edge trig-
gered). /NMI has a higher priority than /INT and is always
recognized at the end of an instruction, regardless of the
state of the interrupt enable flip-flops. This signal forces
CPU execution to continue at location 0066H.
/INT0. Maskable Interrupt Request 0 (Input, active Low).
This signal is generated by external I/O devices. The CPU
will honor this request at the end of the current instruction
cycle as long as the /NMI and /BUSREQ signals are
inactive. The CPU acknowledges this interrupt request
with an interrupt acknowledge cycle. During this cycle,
both the /M1 and /IORQ signals will become active.
/INT1, /INT2. Maskable Interrupt Requests 1 and 2 (inputs,
active Low). This signal is generated by external I/O
devices. The CPU will honor these requests at the end of
the current instruction cycle as long as the /NMI, /BUSREQ,
and /INT0 signals are inactive. The CPU will acknowledge
these interrupt requests with an interrupt acknowledge
cycle. Unlike the acknowledgment for /INT0, during this
cycle neither the /M1 or /IORQ signals will become active.
These pins may be programmed to provide active low
level, rising or falling edge interrupts. The level of the
external /INT1 and /INT2 pins may be read through bits
PC6 and PC7 of parallel port C.
DS971890301
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