Z80189 Datasheet, PDF (84/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
PC MAILBOX DATA REGISTERS (Continued)
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
3. The rising edge of HDRQ causes the 8237 DMA
controller to begin an I/O-read, memory-write DMA
bus cycle on the ISA bus at the end of the current PC
bus cycle. The PC asserts /HDACK low to acknowl-
edge the DMA request.
4. Z189 hardware forces HDRQ inactive low on the
leading (falling) edge of /HRD during the /HDACK
cycle. Note that the HDREQ register is not to be
cleared yet, since the DMA cycle has not completed.
5. The PC asserts /HRD low while /HDACK is still active
low, causing Z189 hardware to enable the latched
HDMAR byte onto HD[0:7].
6. While Z189 hardware holds valid data on the ISA bus,
the PC does its memory-write half of the DMA cycle.
On the trailing (rising) edge of /HRD, Z189 hardware
disables the output of the HDMAR register, putting
HD[0:7] in high impedance state. On this same edge,
hardware clears the HDREQ register bit. Note: /HDDIS
will go low while the HDMAR register is accessed on
the ISA bus.
7. Z180 software polls the HDREQ bit until it's 0, then
continues with step 0 for the next byte.
PC DMA Read will not be stopped as with the case for PC
DMA Write if the HDREQ handshake is not met. If software
fails to see HDREQ reset soon after making the DMA
request (because /HDACK remains inactive high), Z180
software should clear HDREQ and HDMAE and configure
the data pump to stop the PC DMA Read.
Clear HDREQ bit:
Reset
OR I/O write 0 to HDREQ bit in HMC register
OR (Rising edge of (/HRD and /HWR) while /HDACK=0)
Drive HDRQ pin active high:
HDREQ bit = 1 while HDMAE=1
Drive HDRQ pin inactive low:
Reset
OR /HDACK=0
OR HDREQ bit = 0
Latch PC DMA Write data to HDMAT register:
HDMAE=1
AND /HDACK=0
AND /HWR=0
Drive PC DMA Read data from HDMAR register:
HDMAE=1
AND /HDACK=0
AND /HRD=0
Selectable DMA Channels
The Z189 features jumperless selection of PC DMA chan-
nels. On the 8-bit PC/XT bus, DMA channels 0 and 3 are
generally available, therefore reference designs may con-
nect to those. 2 HDREQ bits and 2 HDMAE Enable bits are
used to enable which PC DMA Channel is to be imple-
mented. In addition, there are two additional bits which
allow for the multiplexing of PC DMA Mailbox functions with
Bus Mastering and Z180 peripheral functions.
Logic Equations for PC DMA Read/Write
PC DMA Mailbox Pin Designations
This section summarizes the significant events for PC DMA
Read/Write that was explained in the previous sections.
This section can be used as a quick check of the circuit
implementation.
Set HDREQ bit:
I/O write 1 to HDREQ bit in HMC register.
The four request/acknowledge pins will be designated as
follows, and are assigned the following QFP pins as shown
below:
HDRQ, pin 50, output (mux with RTS0)
/HDACK0, pin 43, input (mux with CKA0 and /DREQ0)
HDRQ1, pin 97, output (mux with /BUSACK)
/HDACK1, pin 98, input (mux with /BUSREQ)
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