Z80189 Datasheet, PDF (97/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
INTERRUPT EDGE/PIN MUX REGISTERS (Continued)
Bit 0 A ‘1’ selects 16 cycle wait delay on recovery from Halt
if bit 5 of the Z80189 Enhancements Register Z180 MPU
Address D9H is set to zero. A ‘0’ selects no wait delay on
Halt recovery. The definition of Halt recovery is as follows.
If this mode is selected the following pins assume the
following states during halt and during the recovery, whether
it is in Halt, SLP, IDLE or STBY Modes:
Address
Data Bus
/RD
/WR
/MREQ
/M1
ST
/IORQ
/BUSACK
/RFSH
/IOCS1
/IOCS2
HDRQ0
HDRQ1
=Z
=Z
=Z
=Z
=Z
=1
=1
=1
= 1 (1)
= 1 (2)
= Z (3)
=Z
= Z (3)
= Z (3)
Note 1. This assumes that BUSREQ is not activated during
the halt.
Note 2. This assumes that the refresh is not enabled. This
would not be a logical case since the address bus
is tri-stated during the Halt mode.
Note 3. This is only true if the function is enabled.
The Halt recovery mode is implemented by applying wait
states to the next cpu operation following the exit from halt.
All signals listed above are forced to their specified state
(unless otherwise noted) during halt and also during the
recovery state. Sixteen cycles after the halt pin goes high
the signals are released to their normal state. Then eight
wait states are inserted to allow proper access to accom-
modate slow memories.
Z80189 ENHANCEMENTS REGISTER (Z180 MPU ADDRESS D9H)
Bit 7 Forced /ROMCS Memory Boundary. When this bit is
set to 1, it will force the /ROMCS boundary. A19 will be
connected directly to /ROMCS. /ROMCS will then be
asserted from 00000H-7FFFFH. When this bit is cleared,
/ROMCS will be accessed under the programmed ad-
dress decoder range. This bit is 0 upon rest.
Note: In this mode, chip select assertion is NOT depen-
dent on /MREQ assertion. During Sleep, /ROMCS will be
forced inactive high.
Bit 6 Forced /RAMCS Memory Boundary. When this bit is
set to 1, it will force the /RAMCS boundary. /A19 will be
connected to /RAMCS. /RAMCS will then be asserted from
8000H-FFFFFH. When this bit is cleared,
/RAMCS will be accessed under the programmed address
decoder range. This bit is 0 upon reset.
Note: In this mode, chip select assertion is NOT depen-
dent on /MREQ assertion. During sleep, /RAMCS is forced
inactive.
Note: When using forced ROM boundary without forced
RAM boundary, or forced RAM boundary without forced
ROM boundary, contention is possible (both /ROMCS &
/RAMCS active). Care should be taken when program-
ming memory boundaries such that there is no overlap.
Bit 5 Force Z180 Halt Mode (Write/Read). MPU Signals
are the same as Z180 during HALT modes. This allows
bus acknowledge cycles during Z189 HALT modes.
Bit 1:4 Reserved
Bit 0 PHI Output Disable. When this bit is set, the PHI
output is not driven by the system clock. The PHI output will
be forced high in this mode. On production boards that do
not use the PHI output, this feature can be used to reduce
EMI. When this bit is reset, the system clock is output to PHI
pin. This bit is reset by default. This feature is not usable in
EV mode 1 (emulation adapter) or EV mode 2 (emulation
probe).
When using the forced memory boundaries, the memory
access time requirement is improved. The improved
Memory access time equation is shown below:
ACC Time < (2 + WS) *clkperiod-Tad-Tdrs
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