Z80189 Datasheet, PDF (40/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
STANDBY Mode
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
The Z8S180 has been designed to save power. Two low-
power programmable power-down modes have been
added; STANDBY mode and IDLE mode. The
STANDBY/IDLE mode is selected by multiplexing D6 and
D3 of the CPU Control Register (CCR, I/O Address = 1FH).
To enter STANDBY mode:
1. Set D6 and D3 to 1 and 0, respectively.
2. Set the I/O STOP bit (D5 of ICR,
I/O Address = 3FH) to 1.
3. Execute the SLEEP instruction.
When the part is in STANDBY mode, it behaves similar to
the SYSTEM STOP mode which currently exists on the
Z80180, except that the STANDBY mode stops the clock
oscillator, internal clocks and reduces the power con-
sumption to a minimum.
Since the clock oscillator has been stopped, a restart of the
oscillator requires a period of time for stabilization. An 18-
bit counter has been added in the Z8S180 to allow for
oscillator stabilization. When the part receives an external
IRQ or BUSREQ during STANDBY mode, the oscillator is
restarted and the timer counts down 2¹⁷ counts before
acknowledgment is sent to the interrupt source.
The clocking is resumed within the Z8S180 and at the
system clock output after /RESET is asserted when the
crystal oscillator is restarted, but not yet stabilized.
STANDBY Mode Exit with BUS REQUEST
Optionally, if the BREXT bit (D5 of CPU Control Register) is
set to 1, the Z8S180 exits STANDBY mode when the
/BUSREQ input is asserted; the crystal oscillator is then
restarted. An internal counter automatically provides time
for the oscillator to stabilize, before the internal clocking
and the system clock output of the Z8S180 are resumed.
The Z8S180 relinquishes the system bus after the clocking
is resumed by:
- Tri-State the address outputs A19 through A0.
- Tri-State the bus control outputs /MREQ, /IORQ,
/RD and /WR.
- Asserting /BUSACK.
The Z8S180 regains the system bus when /BUSREQ is
deactivated. The address outputs and the bus control
outputs are then driven High; the STANDBY mode is
exited.
The recovery source needs to remain asserted for duration
of the 2¹⁷ count, otherwise standby will be resumed.
The following is a description of how the part exits STANDBY
for different interrupts and modes of operation.
STANDBY Mode Exit with /RESET
If the BREXT bit of the CPU Control Register (CCR) is
cleared, asserting the /BUSREQ would not cause the
Z8S180 to exit STANDBY mode.
If STANDBY mode is exited due to a reset or an external
interrupt, the Z8S180 remains relinquished from the sys-
tem bus as long as /BUSREQ is active.
The /RESET input needs to be asserted for a duration long
enough for the crystal oscillator to stabilize and then exit
from the STANDBY mode. When /RESET is de-asserted, it
goes through the normal reset timing to start instruction
execution at address (logical and physical) 0000H.
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DS971890301