Z80189 Datasheet, PDF (76/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
TRANSMIT AND RECEIVE TIMERS (Continued)
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
765 43210
1 11 1 11 11
Receiver Time Constant
Figure 88. Receiver Time Constant Register
(Z180 MPU Address XXFB)
When the Z180 MPU writes to the Receive Buffer register
and the Receive Timer is enabled, the Receive Timer is
loaded with the Receiver Time Constant, the timer is
enabled and counts down to zero. When the timer reaches
zero, the Data Ready bit in the Line Status Register is set.
As with the Transmit Timer the Data Ready bit is also
mirrored. Immediately upon a write to the Receive Buffer,
the mirrored bit is set to let the Z180 MPU know that the byte
has already been written. If the timer is not enabled, then
both Data Ready bits are set immediately upon a write to
the Receive Buffer. The FIFO mode of operation is similar
in that the status to the PC is always delayed by the time
required for each character written to the FIFO by the Z180.
The effect is that the PC will not see a FIFO trigger level or
DMA request faster than would occur with a true UART
when the delay feature is enabled.
16550 MIMIC REGISTERS
The Z80189 contains a register set for interfacing with the
PC/XT/AT. The registers are:
Receiver Buffer Register
Transmit Holding Register
Interrupt Enable Register
Interrupt Identification Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratch Register
Divisor Latch Least Significant/Most Significant Bytes
FIFO Control Register
MIMIC Modification Register
Receive Buffer Register
When the Z180 has assembled a byte of data to pass to the
PC/XT/AT, it places it in the Receiver Buffer Register. If the
Received Data Available interrupt is enabled, then an
interrupt is generated for the PC/XT/AT and the Data
Ready bit is set (if the Receiver Timer is enabled, the
interrupt and setting of the Data Ready bit is delayed until
after the timer times out). Also, the shadow bits of the Line
Status Register are transferred to their respective bits
when the Z180 MPU writes to the Receiver Buffer Register
(see Line Status Register Bits 1, 2, 3 and 4). This allows a
simultaneous setting of error bits when the data is written
to the Receiver Buffer Register. In FIFO mode, this address
is used to read (PC) and write (Z180) the Receiver FIFO.
These registers are used to emulate the 16550 UART. The
PC/XT/AT can access these registers just as if it was
interfacing with the 16550 UART. This allows the Z80189 to
be software compatible with existing Z80189 modem
software.
765 43210
X XX X XX XX
Receiver Buffer
Register
PC Read Only,
(Address 00h, DLAB=0, R/W=Read)
(Z180 MPU Write Only, Address xxF0H)
Figure 89. Receiver Buffer Register
76
DS971890301