Z80189 Datasheet, PDF (69/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Z80189 MIMIC SYNCHRONIZATION CONSIDERATIONS
Because of the asynchronous nature of the FIFO’s on the
MIMIC, some scheme of synchronization must be pro-
vided to prevent conflict from the dual port accesses of the
MPU and the PC.
To solve this problem, I/O to the FIFO is buffered, the
buffers allowing both PC and MPU to access the FIFO
asynchronously. Read and Write requests are then syn-
chronized by means of the MPU clock. Incoming signals
are buffered in such a way that meta-stable input levels will
be stabilized to valid 1 or 0 levels. Actual transfers to and
from the buffers from and to the FIFO memory are timed by
the MPU clock. ALU evaluation is performed on a different
phase than the transfer to ensure stable pointer values.
Another potential problem is that of simultaneous access
of the MPU and PC to any of the various ‘mailbox’ type
registers. This is solved by dual buffering of the various
read/write registers. During a read access by either MPU
or PC to a mailbox register, the data in the buffered slave
register is not permitted to change. Any write that might
take place during this time will be stored in the input of the
master register. The corresponding status/interrupt will be
reset as appropriate based on the write having followed
the read to the register. For example, the IUS/IP bit for the
LCR write will not be cleared by the MPU read of the LCR
if a simultaneous write to the LCR by the PC takes place.
Instead the LSR data will change after the read access and
IUS/IP bit 3 will remain at logic 1.
DOUBLE BUFFERING FOR THE TRANSMITTER IN 16450 MODE
The Z80189 implements double buffering for the transmit-
ter in 16450 mode and sets the TEMT bit in the LSR
Register automatically.
If character delay emulation is being used (see Figure 79):
1. The PC THRE bit in the LSR Register is set when the
THR Register is empty;
2. PC Host writes to the 16450 THR Register;
3. Whenever the Z80189 TSR buffer is empty and one
character delay timer is in a time out state, the byte
from the THR Register is transferred to the TSR buffer;
4. Restart character delay timer (timer reloads and counts
down) with byte transfer from THR Register to the TSR
buffer;
7. TEMT bit in LSR Register for MPU is set with no delay
whenever the TSR buffer is empty;
8. When the TSR buffer is read by MPU and THR Register
is empty and one character delay timer reaches zero
the TEMT bit in the LSR Register for Host is set from 0
to 1.
The PC THRE bit in the LSR Register is reset whenever the
THR Register is full and set whenever THR Register is
empty. MPU IREQ and DMA Request for the transmit data
is triggered whenever the TSR buffer is full and cleared
whenever TSR buffer is empty.
If character delay emulation is not used the TEMT bit in the
LSR Register is set whenever both the THR Register and
the TSR buffer are both empty. The Host TEMT bit is clear
if there is data in either the TSR buffer or THR Register.
5. Whenever the TSR buffer is full, the TEMT bit in LSR Disable this feature when 16550 FIFO mode is enabled.
Register for MPU is reset with no delay;
6. MPU reads TSR buffer;
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