Z80189 Datasheet, PDF (41/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
STANDBY Mode Exit with External Interrupts
STANDBY mode can be exited by asserting input /NMI.
The STANDBY mode may also exit by asserting /INT0,
/INT1 or /INT2, depending on the conditions specified in
the following paragraphs.
/INT0 wake-up requires assertion throughout duration of
clock stabilization time (2¹⁷ clocks).
If the External Maskable Interrupt input is not active when
clocking resumes, the Z8S180 will not exit STANDBY
mode. If the Non-Maskable Interrupt (/NMI) is not active
when clocking resumes, the Z8S180 still exits the STANDBY
mode even if the interrupt sources go away before the
timer times out, because /NMI is edge-triggered. The
condition is latched internally once /NMI is asserted Low.
IDLE Mode
If exit conditions are met, the internal counter provides time
for the crystal oscillator to stabilize, before the internal
clocking and the system clock output within the Z8S180
are resumed.
IDLE mode is another power-down mode offered by the
Z8S180. To enter IDLE mode:
1. Set D6 and D3 to 0 and 1, respectively.
1. Exit with Non-Maskable Interrupts
If /NMI is asserted, the CPU begins a normal NMI interrupt
acknowledge sequence after clocking resumes.
2. Set the I/O STOP bit (D5 of ICR,
I/O Address = 3FH) to 1.
3. Execute the SLEEP instruction.
2. Exit with External Maskable Interrupts
If an External Maskable Interrupt input is asserted, the CPU
responds according to the status of the Global Interrupt
Enable Flag IEF1 (determined by the ITE1 bit) and the
settings of the corresponding interrupt enable bit in the
Interrupt/Trap Control Register (ITC: I/O Address = 34H):
a. If an interrupt source is disabled in the ITC, asserting
the corresponding interrupt input would not cause the
Z8S180 to exit STANDBY mode. This is true regardless
of the state of the Global Interrupt Enable Flag IEF1.
b. If the Global Interrupt Flag IEF1 is set to 1, and if an
interrupt source is enabled in the ITC, asserting the
corresponding interrupt input causes the Z8S180 to
exit STANDBY mode. The CPU performs an interrupt
acknowledge sequence appropriate to the input be-
ing asserted when clocking is resumed if:
- The interrupt input follows the normal interrupt
daisy chain protocol.
- The interrupt source is active until the acknowledge
cycle is completed.
When the part is in IDLE mode, the clock oscillator is kept
oscillating, but the clock to the rest of the internal circuit,
including the CLKOUT, is stopped completely. IDLE mode
is exited in a similar way as STANDBY mode, i.e., RESET,
BUS REQUEST or EXTERNAL INTERRUPTS, except that
the 2¹⁷bit wake-up timer is bypassed; all control signals are
asserted eight clock cycles after the exit conditions are
gathered.
STANDBY-QUICK RECOVERY Mode
STANDBY-QUICK RECOVERY mode is an option offered
in STANDBY mode to reduce the clock recovery time in
STANDBY mode from 2¹⁷ clock cycles (6.5 ms at 20 MHz)
to 2⁶clock cycles (3.2 µs at 20 MHz). This feature can only
be used when providing an oscillator as clock source.
To enter STANDBY-QUICK RECOVERY mode:
1. Set D6 and D3 to 1 and 1, respectively.
2. Set the I/O STOP bit (D5 of ICR,
I/O Address = 3FH) to 1.
3. Execute the SLEEP instruction.
c. If the Global Interrupt Flag IEF1 is disabled, i.e., reset
to 0, and if an interrupt source is enabled in the ITC,
asserting the corresponding interrupt input will still
cause the Z8S180 to exit STANDBY mode. The CPU
will proceed to fetch and execute instructions that
follow the SLEEP instruction when clocking is re-
sumed.
When the part is in STANDBY-QUICK RECOVERY mode,
the operation is identical to STANDBY mode except when
exit conditions are gathered, i.e., RESET, BUS REQUEST
or EXTERNAL INTERRUPTS; the clock and other control
signals are recovered sooner than the STANDBY mode.
Note: If STANDBY-QUICK RECOVERY is enabled, the
user must make sure stable oscillation is obtained within
64 clock cycles.
DS971890301
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