Z80189 Datasheet, PDF (65/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
16550 MIMIC FIFO DESCRIPTION
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
The receiver FIFO consists of a 16-word FIFO capable of
storing eight data bits and three error bits for each charac-
ter stored (Figure 77). Parity error, Framing error and Break
detect bits are stored, along with the data bits, by copying
their value from three shadow bits, which are write only bits
for the Z80180 MPU LSR address. The three shadow bits
are cleared after they are copied to the FIFO memory. In
FIFO mode, to write error bits into the receiver FIFO, the
MPU must first write the Parity, Framing and Break detect
status to the Line Status Register (shadow bits) and then
write the character associated into the receiver buffer. The
data and error bits will then move into the same address in
the FIFO. The error bits become available to the PC side of
the interface when that particular location becomes the
next address to read (top of FIFO). At that time they may
either be read by the PC by accessing them in the LSR, or
they may cause an interrupt to the PC interface if so
enabled. The error bits are set by the error status of the byte
at the top of the FIFO but may only be cleared by reading
the LSR. If successive reads of the receiver FIFO are
performed without reading the LSR, the status bits will be
set if any of the bytes read have the respective error bit set.
The PC interface may be interrupted when 1, 4, 8 or 14
bytes are available in the receiver FIFO by setting bits 6
and 7 in the FCR (FIFO Control Register, PC address 02h
to the appropriate value. If the FIFO is not empty, but below
the above trigger value, a time-out interrupt is available if
the receiver FIFO is not written by the MPU or read by the
PC by an interval determined by the Character Time-out
Timer. This is an additional Timer with MPU access only
which is used to emulate the 16550 4 character time-out
delay. The timer receives the BRG as its input clock.
Software must determine the correct values to program
into the Receiver Time-out register and the BRG to achieve
the correct delay interval for time-out. These interrupts are
cleared by the FIFO reaching the trigger point or by
resetting the Time-out interval timer by FIFO MPU write or
PC read access.
With FIFO mode enabled, the MPU is interrupted when the
receiver FIFO is empty, corresponding to bit 5 being set in
the IUS/IP register (MPU access only). This bit corre-
sponds to a PC read of the receiver buffer in non-FIFO
(16450) mode. The interrupt source is cleared when the
FIFO becomes non-empty or the MPU reads the IUS/IP
register.
The transmitter FIFO is a 16 byte FIFO with PC write and
MPU read access (Figure 78). In FIFO mode, the PC will
receive an interrupt when the transmitter becomes empty
corresponding to bit 5 being set in the LSR. This bit and the
interrupt source are cleared when the transmitter FIFO
becomes non-empty or the IIR register is read by the PC.
On the MPU interface, the transmitted data available can
be programmed to interrupt the MPU on 1, 4, 8 or 14 bytes
of available data by seeing the appropriate value in the
MPU FSCR control register (MPU write only XXECH) bits 6
and 7. A time-out feature exists, Transmitter Time-out
Timer, which is an additional 8 bit timer with BRG as the
input source. If the transmitter FIFO is non-empty and no
PC write or MPU read of the FIFO has taken place within the
timer interval, a time-out will occur causing a correspond-
ing interrupt to the MPU.
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